1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a test structure capable of providing feedback information during a chemical mechanical polishing (CMP) process.
2. Description of the Related Art
CMP is widely used to planarize and generally remove process layers on semiconductor wafers. CMP typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to remove and/or planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted or above a semi-rigid linearly-moving belt on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be dispersed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, a surface of a process layer formed above the wafer is mechanically and chemically polished.
A variety of systems have been proposed to determine an endpoint of the polishing process. For example, some systems estimate the time needed to polish the surface of the wafer to a desired depth. As is to be expected, any variations in the chemical or mechanical make up of the slurry, the pad, or the wafer may cause the amount of time needed to polish to the desired depth to vary dramatically.
Other systems rely on variations in resistance as an indication that the polishing process has reached the desired level. That is, as the polishing process removes one layer and begins to remove an underlying layer, the resistance to the polishing process may be seen to vary. For example, current applied to a motor that drives the polishing pad may change as the polishing process moves into the underlying layer. This system is not effective where the underlying layer has a similar resistance to the polishing process. Further, this system also suffers from shortcomings arising out of the fact that resistance variations may not be solely attributed to changes in the type of material being processed. Variations in the slurry or polishing pad may also affect resistance to the polishing process.
Additional systems that measure the chemical make up of the residue from the polishing process have also been used to detect polish endpoint. These systems look for the presence of certain materials unique to the underlying layer in the residue of the polishing process. Once these materials are observed, the system assumes that the polishing process has reached the underlying layer and should be discontinued. This system also suffers from certain shortcomings. For example, nonuniform polishing may go undetected. That is, the underlying layer may be reached by the polishing process in some areas, while other areas remain with significant portions of the overlying area still covering the underlying area. The residue may not reflect this nonuniform polishing.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a test structure in a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region.
In another aspect of the present invention, a method is provided for forming a test structure in a semiconductor device. A first process layer is formed above a first structure layer, and first and second openings are formed in the first process layer. At least one of the first and second openings has a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. Material is deposited in the first and second openings including the tapered region.
In yet another aspect of the present invention, a method for controlling a polishing process of a semiconductor device is provided. A first process layer is formed above a first structure layer. First and second openings are formed in the first process layer, with at least one of said first and second openings having a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. Material is deposited in the first and second openings including the tapered region. The first process layer and the material deposited in the first and second openings is polished. The spacing X between the plurality of the openings at the polished surface of the first process layer is measured and compared to a desired spacing. The polishing process of the first process layer and the material deposited in the first and second openings continues in response to the measured spacing X being less than the desired spacing.